Overview
CH568 is a high-performance MCU with 32-bit reduced instruction sets. The system clock frequency can be up to 120MHz. The chip integrates peripheral sources, such as high-speed USB controller, SATA2.0 controller and severral SDIO controllers. CH568 provides two encryption/decryption algorithms (SM4 and AES), and supports 8 types of encryption/decryption modes. CH568 can be widely used in high-speed transfer, information security and other applications.
System Block Diagram
Features
32-bit RISC instruction sets, 120MHz system clock frequency.
192KB CodeFlash, 32KB SRAM, 32KB DATA Flash.
SATA host/device controller.
USB2.0 high-speed master/slave interface (built-in PHY), support DMA.
4 SDIO interfaces.
Support SM4/AES encryption algorithms, 8 types of encryption modes.
4 UARTs, 2 SPIs.
Low-power Sleep mode. Support wake up parts of GPIOs, USB, SATA signals.
7-channel PWM. 3 x 26-bit timers.
Unique 64-bit ID.
Package: LQFP48.