PCI Bus Interface Chip: CH365


CH365 is a universal interface chip that connects to PCI bus, supports I/O port mapping, memory mapping, extended ROM and interrupts. CH365 converts high-speed PCI bus into an easy-to-use 8-bit active parallel interface which similar to ISA bus. It can be used for making low-cost PCI bus-based computer cards, and upgrade ISA bus card to PCI card. Compared with other popular bus, PCI is faster, real-time, better on control, so CH365 is suitable for high-speed real-time I/O control card, communication interface card, data acquisition card, electronic disk, expansion ROM Card and so on. The figure below shows is application block diagram.


  • Realize the slave device interface based on the 32-bit PCI bus.
  • Connects PCI interface into active parallel interface: 8-bit data, 16-bit address, I/O read and write, memory read and write.
  • Supports that can be set for PCI card device ID (Vendor ID, Device ID, Class Code, etc.)
  • Supports write and read I/O port or memory by byte, word and double words.
  • The speed in test can reach to 7MB per second in no burst transfer condition, pulse width is optionally of read and write from 30nS to 450nS.
  • Automatic allocation of I/O base, supports up to 240 bytes of I/O port.
  • Supports local hardware address Re-map function, choose I/O address freely, implement I/O port at the specified address.
  • Upgrade ISA based I/O card to PCI bus directly, without modify the interrelated software of ISA card.
  • Direct mapping supports capacity of 32KB memory SRAM or expansion ROM (Boot ROM).
  • Supports 64KB or 128KB memory or expansion ROM without adding the external components.
  • Supports expansion ROM boot without hard disk, and supports Flash-memory updated on line.
  • Provides the expansion ROM application subprogram library BRM, which is used to display user interface and deal the data under BIOS.
  • Supports low active local interrupt request, and supports interrupt sharing.
  • Provides two-wire serial master interface, can hang serial EEPROM similar with 24C0X.
  • Built-in 4uS to 1mS hardware timing unit, as delay reference for software operation.
  • Big pin interval (0.8mm) PQFP-80 package, compatible with CH361 pins, replace directly.
  • Driver supports Windows 98/Me/2000/XP/Vista/7/8/8.1/10/SERVER 2003/2008/2012/2016 and Linux, provide application API through the DLL.
  • The chip can work itself and upgrade ISA based card without driver.
  • Several patented technologies, easy to use and cost is low.